Theses most similar to those of author Chou, Paul L. (Paul Lee)

Low power ROM generation (1996) read it

Design of a 3-dimension FPGA

Lajevardi, Payam (2005)

  • Advisor: Anantha P. Chandrakasan
  • Department of Electrical Engineering and Computer Science
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Microprocessor energy characterization and optimization through fast, accurate, and flexible simulation

Krashinsky, Ronny (Ronny Meir), 1978- (2001)

  • Advisor: Krste Asanović
  • Department of Electrical Engineering and Computer Science
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Floating point multiply/add unit for the M-machine node processor

Hartman, Daniel K (1996)

  • Advisor: William J. Dally
  • Department of Electrical Engineering and Computer Science
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Circuit designs for the MAP chip

Chen, Andrew R. (Andrew Raymond) (1997)

  • Advisor: William J. Dally
  • Department of Electrical Engineering and Computer Science
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Scalable SRAM design

Wuu, John J. (John Jung-Sheun) (1997)

  • Advisor: Anantha P. Chandrakasan
  • Department of Electrical Engineering and Computer Science
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An I/O port controller for the MAP chip

Ma, Albert (1997)

  • Advisor: William J. Dally
  • Department of Electrical Engineering and Computer Science
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Ultra-dynamic voltage scalable (U-DVS) SRAM design considerations

Sinangil, Mahmut E. (Mahmut Ersin) (2008)

  • Advisor: Anantha P. Chandrakasan
  • Department of Electrical Engineering and Computer Science
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Fault tolerant, low voltage SRAM design

Sinangil, Yildiz (2010)

  • Advisor: Anantha P. Chandrakasan
  • Department of Electrical Engineering and Computer Science
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Reducing instruction cache energy using gated wordlines

Panich, Mukaya, 1975- (1999)

  • Advisor: Krste Asanović
  • Department of Electrical Engineering and Computer Science
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Use of high-level design information for enabling automation of fine-grained power gating

Agarwal, Abhinav (2014)

  • Advisor: Arvind
  • Department of Electrical Engineering and Computer Science
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