Theses most similar to those of author Ma, Albert

Circuits for high-performance low-power VLSI logic (2006) read it

Optimization of power and delay in VLSI circuits using transistor sizing and input ordering

Tan, Chin Hwee (1994)

  • Advisor: Jonathan Allen
  • Department of Electrical Engineering and Computer Science
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Methodology for circuit optimization

Markle, Kendra L. (Kendra Lys) (1995)

  • Advisor: Srinivas Devadas
  • Department of Electrical Engineering and Computer Science
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A sub-threshold cell library and methodology

Kwong, Joyce Y. S. (Joyce Yui Si) (2006)

  • Advisor: Anantha P. Chandrakasan
  • Department of Electrical Engineering and Computer Science
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Fast CMOS buffering with post-change logic

Simon, Thomas D. (Thomas David) (1994)

  • Advisor: Thoams F. Knight, Jr.
  • Department of Electrical Engineering and Computer Science
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Floating point multiply/add unit for the M-machine node processor

Hartman, Daniel K (1996)

  • Advisor: William J. Dally
  • Department of Electrical Engineering and Computer Science
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Design and implementation of the integer unit datapath of the MAP cluster of the M-machine

Gupta, Parag (1996)

  • Advisor: William J. Dally
  • Department of Electrical Engineering and Computer Science
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Variable supply voltage for low power DSP

Gutnik, Vadim (1996)

  • Advisor: Anantha P. Chandrakasan
  • Department of Electrical Engineering and Computer Science
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Scalable SRAM design

Wuu, John J. (John Jung-Sheun) (1997)

  • Advisor: Anantha P. Chandrakasan
  • Department of Electrical Engineering and Computer Science
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ALA ASIC : a standard cell library for Asynchronous Logic Automata

Green, Forrest Oliver Reece (2010)

  • Advisor: Neil Gershenfeld
  • Department of Electrical Engineering and Computer Science
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Circuit techniques for subthreshold leakage reduction in a deep sub-micron process

Calhoun, Benton H. (Benton Highsmith), 1978- (2002)

  • Advisor: Anantha P. Chandrakasan
  • Department of Electrical Engineering and Computer Science
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An I/O port controller for the MAP chip (1997) read it

SCALE DRAM subsystem power analysis

Bhalodia, Vimal (2005)

  • Advisor: Krste Asanović
  • Department of Electrical Engineering and Computer Science
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Microprocessor energy characterization and optimization through fast, accurate, and flexible simulation

Krashinsky, Ronny (Ronny Meir), 1978- (2001)

  • Advisor: Krste Asanović
  • Department of Electrical Engineering and Computer Science
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A shared bus architecture for a digital signal processor and a microcontroller

Singer, Jonathan Noam (1996)

  • Advisor: Stephen A. Ward
  • Department of Electrical Engineering and Computer Science
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Hoover bus : an input bus optimized for multiple real-time data streams

Wong, Jeffrey J. (Jeffrey Justin) (1996)

  • Advisor: Bove, V. Michael
  • Department of Electrical Engineering and Computer Science
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Design of the configuration and diagnostic units of the MAP chip

Klayman, Klaus (1997)

  • Advisor: William J. Dally
  • Department of Electrical Engineering and Computer Science
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Circuit designs for the MAP chip

Chen, Andrew R. (Andrew Raymond) (1997)

  • Advisor: William J. Dally
  • Department of Electrical Engineering and Computer Science
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Control and application of a pixel-parallel image processing system

Hall, Gary (1997)

  • Advisor: Charles G. Sodini
  • Department of Electrical Engineering and Computer Science
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Fast thread communication and synchronization mechanisms for a scalable single chip multiprocessor

Keckler, Stephen William (1998)

  • Advisor: Dr. William J. Dally
  • Department of Electrical Engineering and Computer Science
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Design decision in the implementation of a raw architecture workstation

Taylor, Michael Bedford, 1975- (1999)

  • Advisor: Anant Agarwal
  • Department of Electrical Engineering and Computer Science
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Use of high-level design information for enabling automation of fine-grained power gating

Agarwal, Abhinav (2014)

  • Advisor: Arvind
  • Department of Electrical Engineering and Computer Science
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