Theses most similar to Load-balanced rendering on a general-purpose tiled architecture (Chen, Jiawen (Jiawen Kevin); 2005) read it

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SIMD column-parallel polygon rendering

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High-performance computing with PetaBricks and Julia

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Auto-tuning on the macro scale : high level algorithmic auto-tuning for scientific applications

Chan, Cy P (2012)

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A technique for compilation to exposed memory hierarchy

Greenwald, Benjamin Eliot, 1975- (1999)

  • Advisor: Saman Amarasinghe
  • Department of Electrical Engineering and Computer Science
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Terapixel image processing and simulation with distributed halide

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Software orchestration of instruction level parallelism on tiled processor architectures

Lee, Walter (Walter Cheng-Wan) (2005)

  • Advisors: Anant Agarwal; Saman Amarasinghe
  • Department of Electrical Engineering and Computer Science
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Store Buffers : implementing single cycle store instructions in write-through, write-back and set associative caches

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  • Advisor: Anant Agarwal
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